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JHL heven
synopsys_mcu
Commits
2504a8b1
Commit
2504a8b1
authored
2 years ago
by
hevenj
Browse files
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Plain Diff
更新15日到21日的修改
parent
06305d1f
Changes
17
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17 changed files
fm/srcipt/fm_flow.tcl
+0
-0
fm/srcipt/fm_flow.tcl
fm/srcipt/fm_setup.tcl
+2
-2
fm/srcipt/fm_setup.tcl
rtl/APB_IP/APB_CAN/canfd_v3_0.v
+1
-1
rtl/APB_IP/APB_CAN/canfd_v3_0.v
rtl/CORE_AHB_CFG/fpga_clock_wrapper.v
+1
-1
rtl/CORE_AHB_CFG/fpga_clock_wrapper.v
rtl/CORE_AHB_PLIC/AHB_PLIC.v
+7
-2
rtl/CORE_AHB_PLIC/AHB_PLIC.v
rtl/CORE_AHB_PLIC/ahb_plic_wrapper.v
+2
-0
rtl/CORE_AHB_PLIC/ahb_plic_wrapper.v
rtl/DUCKCORE/AHB_DuckCore.v
+4
-1
rtl/DUCKCORE/AHB_DuckCore.v
rtl/DUCKCORE/CORE_CPU/DuckCore.v
+3
-0
rtl/DUCKCORE/CORE_CPU/DuckCore.v
rtl/DUCKCORE/CORE_CPU/cpu_fetch_decode.v
+39
-63
rtl/DUCKCORE/CORE_CPU/cpu_fetch_decode.v
rtl/duckcore_def.v
+1
-1
rtl/duckcore_def.v
rtl/duckcore_wrapper.v
+3
-0
rtl/duckcore_wrapper.v
sim/.synopsys_dve_rebuild.tcl
+0
-9
sim/.synopsys_dve_rebuild.tcl
sim/modelsim/transcript
+2280
-2985
sim/modelsim/transcript
syn/script/common_setup.tcl
+4
-4
syn/script/common_setup.tcl
syn/script/dc_flow.tcl
+11
-1
syn/script/dc_flow.tcl
syn/script/dc_savefile.tcl
+4
-0
syn/script/dc_savefile.tcl
syn/script/duckcore_wrapper_cell.sdc
+1
-1
syn/script/duckcore_wrapper_cell.sdc
with
2363 additions
and
3071 deletions
+2363
-3071
fm/fm_flow.tcl
→
fm/
srcipt/
fm_flow.tcl
View file @
2504a8b1
File moved
This diff is collapsed.
Click to expand it.
fm/fm_setup.tcl
→
fm/
srcipt/
fm_setup.tcl
View file @
2504a8b1
#---------------------------------------------------------
#
逻辑库变量的定义
#
逻辑库变量的定义
# Logical Library Setting
#---------------------------------------------------------
...
...
@@ -8,7 +8,7 @@ set_app_var search_path $LIBRARY_PATH
#---------------------------------------------------------
#
物理库变量的定义
#
物理库变量的定义
# Physical Library Setting
#---------------------------------------------------------
...
...
This diff is collapsed.
Click to expand it.
rtl/APB_IP/APB_CAN/canfd_v3_0.v
View file @
2504a8b1
...
...
@@ -98,7 +98,7 @@
`timescale 1 ns/1 ps
`include "../../duckcore_def.v"
//
`define RST_IN_SENSITIVITY_LIST //
`define RST_IN_SENSITIVITY_LIST //
(* DowngradeIPIdentifiedWarnings="yes" *)
This diff is collapsed.
Click to expand it.
rtl/CORE_AHB_CFG/fpga_clock_wrapper.v
View file @
2504a8b1
...
...
@@ -73,7 +73,7 @@ begin
end
else
begin
if
(
b1553_divcnt
==
4'd
11
)
if
(
b1553_divcnt
==
4'd
9
)
begin
b1553_divcnt
<=
4'h0
;
b1553_1m
<=
~
b1553_1m
;
...
...
This diff is collapsed.
Click to expand it.
rtl/CORE_AHB_PLIC/AHB_PLIC.v
View file @
2504a8b1
...
...
@@ -44,6 +44,7 @@ module AHB_PLIC (
input
[
2
:
0
]
cpu_ex_jump_type_i
,
input
mstatus_MIE_i
,
input
cpu_stall_i
,
input
hard_nest_en_i
,
input
ex_int_nten_i
,
input
ex_int_lose_i
,
...
...
@@ -106,6 +107,8 @@ endfunction
`define
IRQ_CTRL_STS 16
'
h0110
//控制及状态寄存器
`define
IRQ_SHIEL0_ADDR 16
'
h0114
//中断屏蔽寄存器
0
地址
`define
IRQ_SHIEL1_ADDR 16
'
h0118
//中断屏蔽寄存器
1
地址
`define
IRQ_IP0_ADDR 16
'
h011C
//中断
IP
寄存器
0
地址
`define
IRQ_IP1_ADDR 16
'
h0120
//中断
IP
寄存器
1
地址
`define
IRQ_NUM 8
'
d32
//外设中断源数量
`define
IRQ_PRIORITY_MAX 8
'
d31
//外设中断最大优先级
...
...
@@ -1006,6 +1009,8 @@ always @ (posedge HCLK or negedge HRESETn)
`IRQ_THRESHOLD_ADDR
:
HRDATA_r
<=
{
24'd0
,
irq_threshold
}
;
`IRQ_SHIEL0_ADDR
:
HRDATA_r
<=
irq_shiel
[
31
:
0
];
//`IRQ_SHIEL1_ADDR: HRDATA_r <= irq_shiel[63:32];
//`IRQ_IP0_ADDR: HRDATA_r <= irq_ip_level_5[31:0];
//`IRQ_IP1_ADDR: HRDATA_r <= irq_ip_level_5[63:32];
`IRQ_CTRL_STS
:
HRDATA_r
<=
{
current_st
,
int_run_num
,
int_num
,
irq_id
}
;
`IRQ_ID_ADDR
:
HRDATA_r
<=
{
24'd0
,
irq_id
}
;
default:
HRDATA_r
<=
HRDATA_r
;
...
...
@@ -1104,11 +1109,11 @@ always @ (posedge HCLK or negedge HRESETn)
begin
int_run_num
<=
4'd0
;
end
else
if
(
ahb_rd
&&
ahb_addr_w
==
`IRQ_ID_ADDR
&&
int_run_num
<
4'd8
&&
current_st
==
ST_WAIT_RD
)
else
if
(
ahb_rd
&&
ahb_addr_w
==
`IRQ_ID_ADDR
&&
int_run_num
<
4'd8
&&
current_st
==
ST_WAIT_RD
&&
hard_nest_en_i
)
begin
int_run_num
<=
int_run_num
+
1'b1
;
end
else
if
(
ahb_wr
&&
ahb_addr_w
==
`IRQ_ID_ADDR
&&
int_run_num
>
0
&&
(
current_st
==
ST_WAIT_WR
||
current_st
==
ST_RD
||
current_st
==
ST_IDLE
))
else
if
(
ahb_wr
&&
ahb_addr_w
==
`IRQ_ID_ADDR
&&
int_run_num
>
0
&&
(
current_st
==
ST_WAIT_WR
||
current_st
==
ST_RD
||
current_st
==
ST_IDLE
)
&&
hard_nest_en_i
)
begin
int_run_num
<=
int_run_num
-
1'b1
;
end
...
...
This diff is collapsed.
Click to expand it.
rtl/CORE_AHB_PLIC/ahb_plic_wrapper.v
View file @
2504a8b1
...
...
@@ -39,6 +39,7 @@ module ahb_plic_wrapper #
input
[
2
:
0
]
cpu_ex_jump_type_i
,
input
mstatus_MIE_i
,
input
cpu_stall_i
,
input
hard_nest_en_i
,
input
ex_int_nten_i
,
input
ex_int_lose_i
,
// 中断输入信号
...
...
@@ -162,6 +163,7 @@ AHB_PLIC u_AHB_PLIC
.
cpu_ex_jump_type_i
(
cpu_ex_jump_type_i
),
.
mstatus_MIE_i
(
mstatus_MIE_i
),
.
cpu_stall_i
(
cpu_stall_i
),
.
hard_nest_en_i
(
hard_nest_en_i
),
.
ex_int_nten_i
(
ex_int_nten_i
),
.
ex_int_lose_i
(
ex_int_lose_i
),
...
...
This diff is collapsed.
Click to expand it.
rtl/DUCKCORE/AHB_DuckCore.v
View file @
2504a8b1
...
...
@@ -27,10 +27,11 @@ module AHB_DuckCore
output
wire
csr_time_irq_o
,
output
wire
mstatus_MIE_o
,
output
wire
cpu_stall_o
,
output
wire
hard_nest_en_o
,
output
wire
ex_int_nten_o
,
output
wire
ex_int_lose_o
,
input
wire
[
1
:
0
]
boot
,
input
wire
ahb_imem_grant_i
,
input
wire
[
31
:
0
]
ahb_imem_rdata_i
,
input
wire
ahb_imem_ready_i
,
...
...
@@ -290,6 +291,7 @@ module AHB_DuckCore
.
csr_time_irq_o
(
csr_time_irq_w
),
.
mstatus_MIE_o
(
mstatus_MIE_w
),
.
cpu_stall_o
(
cpu_stall_o
),
.
hard_nest_en_o
(
hard_nest_en_o
),
.
ex_int_nten_o
(
ex_int_nten_o
),
.
ex_int_lose_o
(
ex_int_lose_o
),
...
...
@@ -353,6 +355,7 @@ module AHB_DuckCore
.
csr_time_irq_o
(
),
.
mstatus_MIE_o
(
),
.
cpu_stall_o
(
),
.
hard_nest_en_o
(
),
.
ex_int_nten_o
(
),
.
ex_int_lose_o
(
),
...
...
This diff is collapsed.
Click to expand it.
rtl/DUCKCORE/CORE_CPU/DuckCore.v
View file @
2504a8b1
...
...
@@ -53,6 +53,7 @@ module DuckCore
output
reg
csr_time_irq_o
,
output
reg
mstatus_MIE_o
,
output
wire
cpu_stall_o
,
output
reg
hard_nest_en_o
,
output
reg
ex_int_nten_o
,
output
wire
ex_int_lose_o
,
...
...
@@ -841,6 +842,7 @@ assign stall_mem_w = (( (execute_mem_type_w2 == `MEMOP_TYPE_LOAD)
csr_software_irq_o
<=
1'b0
;
csr_time_irq_o
<=
1'b0
;
mstatus_MIE_o
<=
1'b0
;
hard_nest_en_o
<=
1'b0
;
ex_int_nten_o
<=
1'b0
;
ex_int_lose_r
<=
1'b0
;
end
...
...
@@ -849,6 +851,7 @@ assign stall_mem_w = (( (execute_mem_type_w2 == `MEMOP_TYPE_LOAD)
csr_software_irq_o
<=
software_irq_w
;
csr_time_irq_o
<=
time_irq_w
;
mstatus_MIE_o
<=
mstatus_MIE_w
;
hard_nest_en_o
<=
mie_w
[
0
]
;
ex_int_nten_o
<=
ex_int_nten_w
;
ex_int_lose_r
<=
ex_int_lose_w
;
end
...
...
This diff is collapsed.
Click to expand it.
rtl/DUCKCORE/CORE_CPU/cpu_fetch_decode.v
View file @
2504a8b1
...
...
@@ -61,28 +61,20 @@ module cpu_fetch_decode
inst_tri_mod0
<=
32'h00000001
;
inst_addr_tri_mod0
<=
CPU_BOOT_ADDR
;
end
else
if
(
flush_flag_i
)
begin
instcount_en_tri_mod0
<=
1'b0
;
inst_tri_mod0
<=
32'h00000001
;
inst_addr_tri_mod0
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod0
<=
instcount_en_o
;
inst_tri_mod0
<=
inst_o
;
inst_addr_tri_mod0
<=
inst_addr_o
;
end
else
begin
if
(
flush_flag_i
)
begin
instcount_en_tri_mod0
<=
1'b0
;
inst_tri_mod0
<=
32'h00000001
;
inst_addr_tri_mod0
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod0
<=
instcount_en_o
;
end
else
begin
//if(flush_flag_i || (!instcount_en_i) )begin
if
(
!
instcount_en_i
)
begin
instcount_en_tri_mod0
<=
1'b0
;
inst_tri_mod0
<=
32'h00000001
;
inst_addr_tri_mod0
<=
inst_addr_o
;
end
else
begin
instcount_en_tri_mod0
<=
instcount_en_i
;
inst_tri_mod0
<=
inst_i
;
inst_addr_tri_mod0
<=
inst_addr_i
;
end
end
instcount_en_tri_mod0
<=
instcount_en_i
;
inst_tri_mod0
<=
inst_i
;
inst_addr_tri_mod0
<=
inst_addr_i
;
end
end
...
...
@@ -93,28 +85,20 @@ module cpu_fetch_decode
inst_tri_mod1
<=
32'h00000001
;
inst_addr_tri_mod1
<=
CPU_BOOT_ADDR
;
end
else
if
(
flush_flag_i
)
begin
instcount_en_tri_mod1
<=
1'b0
;
inst_tri_mod1
<=
32'h00000001
;
inst_addr_tri_mod1
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod1
<=
instcount_en_o
;
inst_tri_mod1
<=
inst_o
;
inst_addr_tri_mod1
<=
inst_addr_o
;
end
else
begin
if
(
flush_flag_i
)
begin
instcount_en_tri_mod1
<=
1'b0
;
inst_tri_mod1
<=
32'h00000001
;
inst_addr_tri_mod1
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod1
<=
instcount_en_o
;
end
else
begin
//if(flush_flag_i || (!instcount_en_i) )begin
if
(
!
instcount_en_i
)
begin
instcount_en_tri_mod1
<=
1'b0
;
inst_tri_mod1
<=
32'h00000001
;
inst_addr_tri_mod1
<=
inst_addr_o
;
end
else
begin
instcount_en_tri_mod1
<=
instcount_en_i
;
inst_tri_mod1
<=
inst_i
;
inst_addr_tri_mod1
<=
inst_addr_i
;
end
end
instcount_en_tri_mod1
<=
instcount_en_i
;
inst_tri_mod1
<=
inst_i
;
inst_addr_tri_mod1
<=
inst_addr_i
;
end
end
...
...
@@ -125,28 +109,20 @@ module cpu_fetch_decode
inst_tri_mod2
<=
32'h00000001
;
inst_addr_tri_mod2
<=
CPU_BOOT_ADDR
;
end
else
if
(
flush_flag_i
)
begin
instcount_en_tri_mod2
<=
1'b0
;
inst_tri_mod2
<=
32'h00000001
;
inst_addr_tri_mod2
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod2
<=
instcount_en_o
;
inst_tri_mod2
<=
inst_o
;
inst_addr_tri_mod2
<=
inst_addr_o
;
end
else
begin
if
(
flush_flag_i
)
begin
instcount_en_tri_mod2
<=
1'b0
;
inst_tri_mod2
<=
32'h00000001
;
inst_addr_tri_mod2
<=
flush_addr_i
;
end
else
if
(
stall_flag_i
)
begin
instcount_en_tri_mod2
<=
instcount_en_o
;
end
else
begin
//if(flush_flag_i || (!instcount_en_i) )begin
if
(
!
instcount_en_i
)
begin
instcount_en_tri_mod2
<=
1'b0
;
inst_tri_mod2
<=
32'h00000001
;
inst_addr_tri_mod2
<=
inst_addr_o
;
end
else
begin
instcount_en_tri_mod2
<=
instcount_en_i
;
inst_tri_mod2
<=
inst_i
;
inst_addr_tri_mod2
<=
inst_addr_i
;
end
end
instcount_en_tri_mod2
<=
instcount_en_i
;
inst_tri_mod2
<=
inst_i
;
inst_addr_tri_mod2
<=
inst_addr_i
;
end
end
...
...
This diff is collapsed.
Click to expand it.
rtl/duckcore_def.v
View file @
2504a8b1
...
...
@@ -26,7 +26,7 @@
//-------------------------------------------------------------
// 总定义
//-------------------------------------------------------------
`define
FLASH_BIN_LOCALE
"../
test_program
/
test_flow
3
.
bin
"
`define
FLASH_BIN_LOCALE
"../
test_program
/
test_flow
2
.
bin
"
// `define SIM_GPION //仿真,关GPIO(一般使用)
// `define SIM_GPIOY //仿真,开GPIO
...
...
This diff is collapsed.
Click to expand it.
rtl/duckcore_wrapper.v
View file @
2504a8b1
...
...
@@ -448,6 +448,7 @@ module duckcore_wrapper
wire
csr_time_irq_w
;
wire
mstatus_MIE_w
;
wire
cpu_stall_w
;
wire
hard_nest_en_w
;
wire
ex_int_nten_w
;
wire
ex_int_lose_w
;
wire
qei_irq_o0
;
...
...
@@ -1521,6 +1522,7 @@ module duckcore_wrapper
.
csr_time_irq_o
(
csr_time_irq_w
),
.
mstatus_MIE_o
(
mstatus_MIE_w
),
.
cpu_stall_o
(
cpu_stall_w
),
.
hard_nest_en_o
(
hard_nest_en_w
),
.
ex_int_nten_o
(
ex_int_nten_w
),
.
ex_int_lose_o
(
ex_int_lose_w
),
.
boot
(
{
boot1
,
boot0
}
),
...
...
@@ -2106,6 +2108,7 @@ module duckcore_wrapper
.
HRDATA
(
HRDATAS6_w
),
.
cpu_ex_jump_type_i
(
cpu_ex_jump_type_w
),
.
cpu_stall_i
(
cpu_stall_w
),
.
hard_nest_en_i
(
hard_nest_en_w
),
.
ex_int_nten_i
(
ex_int_nten_w
),
.
ex_int_lose_i
(
ex_int_lose_w
),
// 中断输入信号
...
...
This diff is collapsed.
Click to expand it.
sim/.synopsys_dve_rebuild.tcl
deleted
100644 → 0
View file @
06305d1f
# DVE Simulation Rebuild/Restart Options
# Saved on Fri Apr 1 11:08:39 2022
set SIMSETUP::REBUILDOPTION 1
set SIMSETUP::REBUILDCMD
{}
set SIMSETUP::REBUILDDIR
{}
set SIMSETUP::RESTOREBP 1
set SIMSETUP::RESTOREDUMP 1
set SIMSETUP::RESTOREFORCE 1
set SIMSETUP::RESTORESPECMAN 0
This diff is collapsed.
Click to expand it.
sim/modelsim/transcript
View file @
2504a8b1
This diff is collapsed.
Click to expand it.
syn/script/common_setup.tcl
View file @
2504a8b1
#---------------------------------------------------------
#
路径
变量的定义
#
路径变量的定义
# user defined variable for logical library
#---------------------------------------------------------
...
...
@@ -18,12 +18,12 @@ set LIBRARY_PATH [list
$lib_path
\s
ynopsys_lib/smic110/ram_lib/db
\
$lib_path
\s
ynopsys_lib/smic110/gpio_lib/syn
]
#
标准
单元库
#
标准单元库
set STD_LIB_NAME
"sc9tap_logic011_base_rvt"
set TARGET_STD_LIB_FILES
"
$
STD_LIB_NAME
\_
ss_typical_max_1p08v_125c.db"
set SYMBOL_STD_LIB_FILES
"
$
STD_LIB_NAME.sdb"
# RAM库
# RAM
库
set TARGET_RAM_LIB_PVT SS_1.08_125
set TARGET_RAM_LIB_FILES
[
list
\
S011HD2P_X32Y2D16_$TARGET_RAM_LIB_PVT
\.
db
\
...
...
@@ -37,7 +37,7 @@ set TARGET_RAM_LIB_FILES [list
set SYMBOL_RAM_LIB_FILES $TARGET_RAM_LIB_FILES
# GPIO库
# GPIO
库
set TARGET_GPIO_LIB_FILES
"SP013D3WP_V1p7_min.db"
set SYMBOL_GPIO_LIB_FILES $TARGET_GPIO_LIB_FILES
...
...
This diff is collapsed.
Click to expand it.
syn/script/dc_flow.tcl
View file @
2504a8b1
...
...
@@ -91,7 +91,7 @@ set_app_var hdlin_check_no_latch true
#set_app_var hdlin_merge_nested_conditional_statements true
set test_default_scan_style multiplexed_flip_flop
#set hlo_resource_allocation area
set_host_option -max_cores
2
set_host_option -max_cores
4
...
...
@@ -122,6 +122,7 @@ echo "******Step 3 end ******"
# Read design to DC Memory
#-----------------------------------------------------
echo
"******Step 4 start ******"
set curtime
[
clock seconds
]
# 读取RTL文件 并检查语法
# 激活当前设计模块
...
...
@@ -213,5 +214,14 @@ set design_version "2.0"
source ../script/dc_optimize_strategy.tcl
source ../script/dc_savefile.tcl
set tcl_precision 4
puts
"synthesis time is
[
expr
([
clock seconds
]
- $curtime
)
/60.0/60.0
]
hours"
exit
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syn/script/dc_savefile.tcl
View file @
2504a8b1
...
...
@@ -62,12 +62,16 @@ change_names -rule verilog -hier
write_file -format verilog -hierarchy -output $out_netlist
write_file -format ddc -hierarchy -output $out_ddc
write_sdf $out_sdf
#移除ideal_net后保存sdc,因为PR中没有ideal_net
remove_idela_net
[
all_ideal_nets
]
write_sdc $out_sdc
#-----------------------------------------------------
# Step 9 :
# Save svf file
(
to FM
)
#-----------------------------------------------------
#保存svf文件,用于形式验证
sh cp -f default.svf ../../fm/$save_file
\.
svf
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syn/script/duckcore_wrapper_cell.sdc
View file @
2504a8b1
...
...
@@ -66,7 +66,7 @@
-to [get_pins -filter direction=="in" -of_objects [get_cells -hierarchical -filter name=~*X512Y16D32*]] \
-weight 5 -critical_range 800
group_path -name icache_lru_reg \
-to [get_pins -filter name=="
CK
" -of_objects [get_cells ahb_duckcore_inst/icache_ahb_inst/icache_inst/lru_way?_reg*]] \
-to [get_pins -filter name=="
D
" -of_objects [get_cells ahb_duckcore_inst/icache_ahb_inst/icache_inst/lru_way?_reg*]] \
-weight 5 -critical_range 800
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